The present invention relates to low drop out linear voltage regulators, and, more particularly, to a low drop out linear voltage regulator having efficient frequency compensation using a voltage follower compensation technique.
Power management control systems including voltage regulators are incorporated within portable electronic devices to generate a stable output voltage from a varying input voltage supply. A few of these portable electronic devices include laptop computers, hand-held electronic devices, and cellular phones. The purpose of the voltage regulator is to regulate the external power supplied to the internal circuitry such that the current usage or quiescent power is efficient. The efficiency of battery powered supply systems is directly related to the amount of power dissipated in the voltage regulator. More efficient current usage decreases the size of the required voltage supply. This decrease in voltage supply or battery size enables a designer of the aforementioned portable electronic devices to reduce the weight and size of the portable unit.
A particular type of voltage regulator, the low drop out (LDO) linear voltage regulator is used to reduce power consumption by providing the lowest voltage drop across the linear regulator. The lowest voltage drop the regulator can tolerate before loss of regulation occurs is called the xe2x80x9cdropoutxe2x80x9d voltage. As shown in FIG. 1, a linear voltage regulator 10 conventionally includes an amplifier 14 which compares the output of a voltage reference 12 to a sample of an output voltage supplied by feedback elements 24. The output of the amplifier 14 is coupled to a control terminal 16 of a pass element 18 which serves to xe2x80x9cpassxe2x80x9d current from the unregulated input terminal 20 of the voltage regulator 10, to the regulated output terminal 22 of the voltage regulator 10. The feedback control loop 26 formed by the amplifier 14, pass element 18 and feedback elements 24 acts to force the control terminal 16 of the pass element 18 to a dynamic value that maintains a regulated voltage at the output terminal 22 of the voltage regulator 10.
More specifically, a conventional LDO linear voltage regulator implemented in CMOS includes a power PMOS pass transistor which substitutes for pass element 18 and a voltage divider substituting for feedback element 24. An input voltage Vin is applied to the conduction terminal of the PMOS transistor. A parasitic resistance may be serially connected to output capacitance 28.
This circuit has a dominant pole determined by the output capacitance and dependent upon the load current. Thus, this pole is movable according to load variations and reaches a maximum value when the regulator supplies a maximum output current. This dependence upon the load current of the output pole renders the compensation of this type of voltage regulator complex.
Moreover, instability arises from a second internal pole that is generated by error amplifier 14, if proper compensation is not supplied. The present challenge of power management control systems is that linear voltage regulators often must compromise between robust stability and quiescent power consumption, wherein robust stability is dependent upon the frequency compensation technique.
One such frequency compensation technique is to provide a circuit component, such as the parasitic resistance, to introduce a zero, thereby compensating the effects of the output pole. As such, the output capacitance must be chosen to ensure that the parasitic resistance is kept within a predetermined range of values to provide stability for the voltage regulator. Unfortunately, the parasitic component of the output capacitor and its value may not be determined with high precision.
For this reason, as shown in FIG. 2, an LDO voltage regulator as disclosed in U.S. Pat. No. 6,300,749, which is incorporated by reference, includes Zero Mobile Compensation (ZMC) 54 which provides within the circuit response a zero capable of moving according to the load variations. Variable compensation is implemented within this design without using a compensation resistance to stabilized the amplifier loop of the voltage regulator 50. More specifically, the LDO voltage regulator 50 disclosed includes a zero that is moved toward higher frequencies according to the movement of its output pole.
This approach distinguishes from the previous approach in that a delay phase network 54, introducing a zero and a pole at the lower frequency, is included. The delay phase network 54 in its simplest form may be implemented using an RC network circuit portion. The resistance may be formed by a MOS transistor (not shown). The compensation zero and pole are obtained by the RC network 54, wherein the compensation zero is used to compensate the effect of the second pole in the loop gain. Thereby the circuit is compensated by a zero that moves to higher frequencies proportional to the load current.
Although this approach provides a compensation network with a moving zero, it is dependent upon sensing the load current. In addition, this approach uses a PMOS transistor for a pass element. There, however, exists a need for an NMOS linear voltage regulator that provides a moving zero.
U.S. Pat. No. 6,333,623 discloses an LDO linear NMOS voltage regulator which is incorporated herein. This voltage regulator includes an output stage having a NMOS pass transistor and an over-voltage pass device, such as PMOS discharge transistor or a discharge device which are arranged in complementary voltage follower configurations to both source load current to and sink load current from a regulated output voltage conductor. The NMOS pass transistor and the discharge device are controlled through a single feedback loop.
Although this approach provides a compensation network which limits the movement of the output pole by sinking current at the output of the voltage regulator. This approach focuses on the voltage transient problem. It, however, is unstable or inefficient, depending upon whether the sink current is relatively large or small in comparison to the load current, when an output capacitor Co is large and the load current is small. Therefore, this approach is only valuable within a limited range of the output capacitance wherein the output capacitance is small.
Thus, there exists a need for a LDO linear voltage regulator that overcomes the above described dynamic quiescent current limitation creating an internal zero moving in the same direction and having the same amplitude as the output pole, without sensing a portion of the load current over a large range of capacitance at the output. This voltage regulator must implement the use of a NMOS output power device, wherein the shift of the internal zero is the same amplitude and direction of the shift of the output pole to generate a better frequency compensation. In addition, this voltage regulator must not include current sensing but differential voltage sensing, such that no dynamic quiescent current exists.
The present invention overcomes the above-discussed deficiencies, including, the dynamic quiescent current limitation by creating an internal zero that moves in the same direction and has the same amplitude as that of the output pole without sensing a portion of the load current. The low drop out linear voltage regulator having frequency compensation in accordance with the present invention includes an error amplifier, a NMOS pass transistor, a variable compensation network, and a stabilization circuit. The error amplifier includes a power supply input connected to a first power supply, a non-inverting input coupled to a reference voltage, an inverting input and an output terminal. The NMOS pass transistor includes a source connected to an output terminal of the voltage regulator, a drain coupled to a second power supply, and a gate coupled to the output terminal of the error amplifier. The variable compensation network connects to the error amplifier. More particularly, the variable compensation network may include an RC circuit comprising a resistive transistor and a capacitance coupled in series. The stabilization circuit couples between the NMOS pass transistor and the resistive transistor such that the ratio of the impedance of the NMOS pass transistor to the impedance of the resistive transistor is constant.
Advantages of this design include but are not limited to low drop out linear voltage regulator that provides robust stability with low and invariable quiescent current. This voltage regulator implements the use of a NMOS output power device, wherein the shift of the internal zero is the same amplitude of the shift of the output pole to generate a better frequency compensation. In addition, this voltage regulator includes differential voltage sensing, such that no dynamic quiescent current exists.